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| dc.contributor.author | Bringmann, Oliver | |
| dc.date.accessioned | 2024-05-22T06:50:24Z | |
| dc.date.available | 2024-05-22T06:50:24Z | |
| dc.date.issued | 2024-04-24 | |
| dc.identifier.uri | http://hdl.handle.net/10900/153597 | |
| dc.language.iso | en | de_DE |
| dc.publisher | arXiv | de_DE |
| dc.relation.uri | https://doi.org/10.48550/arXiv.2404.15823 | de_DE |
| dc.subject.ddc | 004 | de_DE |
| dc.title | A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator | de_DE |
| dc.type | Preprint | de_DE |
| utue.personen.roh | Bause, Oliver | |
| utue.personen.roh | Bernardo, Paul Palomero | |
| utue.personen.roh | Bringmann, Oliver |
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