StML: Bridging the Gap between FPGA Design and HDL Circuit Description

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dc.contributor.author Peterson, Dustin
dc.contributor.author Bringmann, Oliver
dc.contributor.author Rosenstiel, Wolfgang
dc.contributor.author Schweizer, Thomas
dc.date.accessioned 2015-05-07T13:42:23Z
dc.date.available 2015-05-07T13:42:23Z
dc.date.issued 2013
dc.identifier.isbn 978-1-4799-2199-7 de_DE
dc.identifier.uri http://hdl.handle.net/10900/63247
dc.language.iso en de_DE
dc.publisher IEEE de_DE
dc.relation.uri https://dx.doi.org/10.1109/FPT.2013.6718366 de_DE
dc.rights info:eu-repo/semantics/closedAccess
dc.subject.ddc 004 de_DE
dc.title StML: Bridging the Gap between FPGA Design and HDL Circuit Description de_DE
dc.type Artikel de_DE
dc.type Konferenzveröffentlichung de_DE
utue.publikation.seiten 278-285 de_DE
utue.personen.roh Peterson, Dustin
utue.personen.roh Bringmann, Oliver
utue.personen.roh Rosenstiel, Wolfgang
utue.personen.roh Schweizer, Thomas
dcterms.isPartOf.ZSTitelID Proceedings International Conference on Field-Programmable Technology de_DE


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