Latency-Optimized Force-directed Process Mapping for MPSoC Architectures

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dc.contributor.author Bringmann, Oliver
dc.contributor.author Rosenstiel, Wolfgang
dc.date.accessioned 2015-04-20T15:39:02Z
dc.date.available 2015-04-20T15:39:02Z
dc.date.issued 2012
dc.identifier.isbn 978-3-8300-6201-1
dc.identifier.uri http://hdl.handle.net/10900/62885
dc.language.iso en de_DE
dc.publisher Hamburg: Kovač de_DE
dc.relation.ispartofseries Schriftenreihe Forschungsergebnisse zur Informatik ; 68 de_DE
dc.rights info:eu-repo/semantics/closedAccess
dc.subject.ddc 004 de_DE
dc.title Latency-Optimized Force-directed Process Mapping for MPSoC Architectures de_DE
dc.type Artikel de_DE
dc.type Konferenzveröffentlichung de_DE
utue.publikation.seiten 145-156 de_DE
utue.personen.roh Schönwald, Timo
utue.personen.roh Ranft, Benjamin
utue.personen.roh Bringmann, Oliver
utue.personen.roh Rosenstiel, Wolfgang
dcterms.isPartOf.ZSTitelID Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen de_DE


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